Hands on Training in VLSI Design
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Duration : 15 Days / 1 Month
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Training Contents :
VLSI Foundational Concepts
Introduction to IC Technology – MOS, PMOS, NMOS, CMOS & BiCMOS technologies- Pass transistor, NMOS Inverter, Various pull ups, CMOS Inverter analysis and design-Gate realization using CMOS-Introduction to Chip Design Process- Evolution of Computer Aided Digital Design - Hardware Description Languages- Introduction to Reconfigurable Hardware -FPGA and CPLD basics- Applications of VLSI.
VHDL Programming
VHDL basics - VHDL levels of abstraction – Structural , Behavioral and dataflow modes of implementation- The VHDL design flow - VHDL design entities - Entity declarations - Architectures –Concurrent signal assignments - Signal assignments with delays – Signal and variable assignments -Sequential statements - VHDL processes - Processes sensitivity lists Conditional statements – loops - selective signal assignments.
System Implementation using VHDL
Subprograms – Functions – Procedures - Differences between functions and procedures - Subprogram declarations – Packages - Package declaration - Package body. Component declarations - Component instantiation - Named port mapping – Positional port mapping –- Modeling hardware in VHDL - VHDL models for multiplexers, Encoders, Decoders, Parity Generators – combinational circuit implementation - Test bench development and VHDL Synthesis.
VERILOG Programming
VERILOG HDL Design Flow-Module Description -Lexical Conventions - Description of Data types - Net - Register- Scalar Data Description - Vector Data Description -Parameters description - Array Description - Gate level Modeling -Dataflow modeling - Behavioral Modeling -Switch level Modeling.
System Implementation using VERILOG
Structured Procedural Statements-Always Statements-Initial Statements. Conditional statements Loops - Block Statements - Parallel block - Sequential block. VERILOG HDL implementation for combinational and Sequential digital circuits – Test Bench Implementation – Synthesis using VERILOG.
List of Deliverables:
1. Free Spartan-3E FPGA Development Board for individual trainee along with download cable and Sotware Disc
2. Hands on Training Program on VLSI Design .
3. Real time Mini Project at the end of the Training Program.
4. Valid Training Certificate useful for employment.
5. Transform into an Interlogicx Certified Professional and get numerous technical resources after the training program.
VLSI Foundational Concepts
Introduction to IC Technology – MOS, PMOS, NMOS, CMOS & BiCMOS technologies- Pass transistor, NMOS Inverter, Various pull ups, CMOS Inverter analysis and design-Gate realization using CMOS-Introduction to Chip Design Process- Evolution of Computer Aided Digital Design - Hardware Description Languages- Introduction to Reconfigurable Hardware -FPGA and CPLD basics- Applications of VLSI.
VHDL Programming
VHDL basics - VHDL levels of abstraction – Structural , Behavioral and dataflow modes of implementation- The VHDL design flow - VHDL design entities - Entity declarations - Architectures –Concurrent signal assignments - Signal assignments with delays – Signal and variable assignments -Sequential statements - VHDL processes - Processes sensitivity lists Conditional statements – loops - selective signal assignments.
System Implementation using VHDL
Subprograms – Functions – Procedures - Differences between functions and procedures - Subprogram declarations – Packages - Package declaration - Package body. Component declarations - Component instantiation - Named port mapping – Positional port mapping –- Modeling hardware in VHDL - VHDL models for multiplexers, Encoders, Decoders, Parity Generators – combinational circuit implementation - Test bench development and VHDL Synthesis.
VERILOG Programming
VERILOG HDL Design Flow-Module Description -Lexical Conventions - Description of Data types - Net - Register- Scalar Data Description - Vector Data Description -Parameters description - Array Description - Gate level Modeling -Dataflow modeling - Behavioral Modeling -Switch level Modeling.
System Implementation using VERILOG
Structured Procedural Statements-Always Statements-Initial Statements. Conditional statements Loops - Block Statements - Parallel block - Sequential block. VERILOG HDL implementation for combinational and Sequential digital circuits – Test Bench Implementation – Synthesis using VERILOG.
List of Deliverables:
1. Free Spartan-3E FPGA Development Board for individual trainee along with download cable and Sotware Disc
2. Hands on Training Program on VLSI Design .
3. Real time Mini Project at the end of the Training Program.
4. Valid Training Certificate useful for employment.
5. Transform into an Interlogicx Certified Professional and get numerous technical resources after the training program.
